1. Field of the Invention
The invention relates to a data transfer protection apparatus, particularly to a data transfer protection apparatus for a flash memory controller.
2. Description of the Prior Art
Due to the fast development of technology, there are many successful products which have already used the flash memory as mass storage medium. The goal is to improve various shortcomings of hard disk storage medium, such as the access speed, output efficiency, lifespan, volume, weight, reliability, shake resistance, carrying convenience and use convenience. Thus, how to improve various properties of mass storage medium is the goal pursued by the industry at present.
There are two kinds of flash memory, there is NOR Type Flash Memory abbreviated as NorFlash, and the other one is NAND Type Flash Memory abbreviated as NandFlash. The NorFlash has the advantages of high reliability and fast random access speed, which is widely used in the application of random access, such as the control memory of BIOS, mobile phone and hard disk driver. NandFlash is more suitable for the storage of pure data and file, such as SmartMedia card, CompactFlash card, PCMCIA ATA card and solid state disk type storage medium.
The SSD (Solid State Drive) is a store system built by NAND Flash Chip, which is used for replacing the conventional hard disk (HDD). It has the characteristics of fast read and write, quiet, low temperature, vibration resistance, power saving, small volume, and light weight, which makes fast development of SSD technique.
The data stored at NAND Flash Chip is protected by any ECC (Error-Correcting-Code) methods, like Reed Solomon or Bose-Chaudhuri-Hocquenghem (BCH). In the BCH method, each data sector of BCH-8 is 512 bytes and parity field is 13 bytes.
The prior BCH encode and decode scheme is shown in FIG. 1. For BCH encode path, the 512 byte data is send into BCH encode module 11, then generate 13 byte parity 112. Total of 525 byte data sector 111 is send into NAND Flash Chip 10 for store. For BCH decode path, the 525 byte data and 13 byte parity 131 stored in NAND Flash Chip 10 is read out and send into BCH decode module 13 for error detection and correction.
Thus, the encode flow, store flow, read flow, and then decode flow is the main BCH protection schema. 13 byte parity has to generate first for the corresponding 512 byte data sector. However at SSD application, there is one situation which cannot generate parity previously. It will make a block (one block is 1024 sectors) erase, and then write partial sectors with desired data. However, read out the whole page (one page is 8 sectors) with erased sectors and written sectors. In this situation, whole un-written sector become 0xFF, no matter the data field or parity field. It means the 512 byte 0xFF data will together with 13 byte 0xFF parity, but this parity is not real. If this data and parity send into BCH decoder, the BCH decoder will become blind and don't have any error detect and correct ability cause of extremely wrong parity.